Shallow trench isolation structures having uniform step heights

ABSTRACT

The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a divisional application of U.S. patentapplication Ser. No. 17/225,249, titled “Shallow Trench IsolationStructures Having Uniform Step Heights,” filed on Apr. 8, 2021, whichclaims the benefit of U.S. Provisional Patent Appl. No. 63/031,245,titled “Shallow Trench Isolation (STI) Structures Having Uniform StepHeights” and filed on May 28, 2020, all of which are incorporated hereinby references in their entireties.

BACKGROUND

With advances in semiconductor technology, there has been increasingdemand for higher storage capacity, faster processing systems, higherperformance, and lower costs. To meet these demands, the semiconductorindustry continues to scale down the dimensions of semiconductordevices. Fin-type field effect transistors (finFETs) have been developedto reduce device footprint and improve device performance. FinFETs areFETs formed over a fin that is vertically oriented with respect to aplanar surface of a wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of this disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the common practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a flow diagram of a method for forming a semiconductorstructure, in accordance with some embodiments.

FIGS. 2-6 illustrate various views of semiconductor fins and STImaterial at various stages of their fabrication process, in accordancewith some embodiments.

FIGS. 7-11 are flow diagrams of methods for forming semiconductorstructures, in accordance with some embodiments.

FIG. 12 is a cross-sectional view of a semiconductor device, inaccordance with some embodiments.

FIG. 13 is an isometric view of a semiconductor device, in accordancewith some embodiments.

Illustrative embodiments will now be described with reference to theaccompanying drawings. In the drawings, like reference numeralsgenerally indicate identical, functionally similar, and/or structurallysimilar elements.

DETAILED DESCRIPTION

The following disclosure provides different embodiments, or examples,for implementing different features of the provided subject matter.Specific examples of components and arrangements are described below tosimplify the present disclosure. These are, of course, merely examplesand are not intended to be limiting. For example, the formation of afirst feature over a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures are disposed between the first and second features, such thatthe first and second features are not in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition does not in itself dictate arelationship between the various embodiments and/or configurationsdiscussed.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. The spatially relative termsare intended to encompass different orientations of the device in use oroperation in addition to the orientation depicted in the figures. Theapparatus may be otherwise oriented (rotated 90 degrees or at otherorientations) and the spatially relative descriptors used herein maylikewise be interpreted accordingly.

The term “nominal” as used herein refers to a desired, or target, valueof a characteristic or parameter for a component or a process operation,set during the design phase of a product or a process, together with arange of values above and/or below the desired value. The range ofvalues is typically due to slight variations in manufacturing processesor tolerances.

In some embodiments, the terms “about” and “substantially” can indicatea value of a given quantity that varies within 5% of the value (e.g.,±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examplesand are not intended to be limiting. The terms “about” and“substantially” can refer to a percentage of the values as interpretedby those skilled in relevant art(s) in light of the teachings herein.

The present disclosure provides methods for forming finFET devices. Theterm “finFET” refers to a FET formed over a fin that is verticallyoriented with respect to a planar surface of a wafer. The term“vertical,” as used herein, refers to nominally perpendicular to thesurface of a substrate. The methods can also be applied towards formingany suitable semiconductor structures, such as horizontal or verticalgate-all-around FETs (GAAFETs).

The performance and scalability of silicon-based transistors is reachingfundamental limits despite the implementation of various enhancementtechniques, such as novel device architectures for enhancedelectrostatic control, transport enhancement by strained channels,improved dopant activation, and parasitic resistance reduction. Asdevice dimensions are scaled down to achieve higher packing density, ithas been a challenge to shrink silicon-based transistors. FinFETs havebeen developed to reduce device footprint and improve deviceperformance. The fins of finFETs may be formed on a semiconductorsubstrate by one or more photolithography processes, includingdouble-patterning or multi-patterning processes. After fins are formed,a layer of shallow trench isolation (STI) material can be deposited onthe substrate and surrounding the fins, providing electrical isolationbetween adjacent fins. Source/drain regions and channel regions of FETscan be formed on portions of the fins that protrude from a top surfaceof the STI material. However, as device dimensions are scaled down,heights of STI material can vary across the wafer and cause fin heightnon-uniformity. For example, due to loading effects, the step height ofSTI material between fins can be greater than the step height of STImaterial formed surrounding an outermost fin of a group of fins.

Various embodiments in the present disclosure describe methods forforming semiconductor devices with substantially uniform STI stepheights. An STI material can be deposited on a substrate and surroundmultiple fins, followed by an etch back process to expose portions ofthe fins. Semiconductor devices formed using the methods disclosedherein can have substantially uniform STI step height across multiplefins. For example, an inner STI step height (e.g., STI step heightbetween adjacent fins) can be substantially equal to an outer STI stepheight (e.g., STI step height for the outermost fin). Multiple etchingprocesses can be used to achieve substantially uniform STI step heights.For example, the etching back process can include etching processes thatremoves STI material at different rates depending on the location of thetargeted STI material. For example, a thermal etching process can etchSTI material formed adjacent to the outermost fin at a greater etchingrate than STI material formed between a pair of adjacent fins. Aplasma-activated etching process can remove STI material at a greaterrate from between adjacent fins than removing STI material that isadjacent to the outermost fin. The etched STI material can be exposed toa radical treatment process, during which surfaces of the etched STImaterial can be exposed to hydrogen radicals. The radical treatmentprocess can adjust the surface profile of the STI material as well asfurther etching the STI material. A combination of multiple etching andtreatment process can provide the benefits of, among other things,substantially uniform STI step height throughout multiple fins. Forexample, inner STI step height can be substantially similar to the outerSTI step heights. In some embodiments, STI step heights can be tunedusing the etching and treatment process to achieve different stepheights based on device needs. For example, inner STI step heights canbe greater than outer step heights.

FIG. 1 is a flow diagram of a method 100 for forming STI material havingsubstantially uniform step height, according to some embodiments. Forillustrative purposes, the operations illustrated in FIG. 1 will bedescribed with reference to the example fabrication process illustratedin FIGS. 2-6 . Operations can be performed in a different order or notperformed depending on specific applications. It should be noted thatmethod 100 may not produce a complete semiconductor device. Accordingly,it is understood that additional processes can be provided before,during, and after method 100, and that some other processes may only bebriefly described herein.

Referring to FIG. 1 , in operation 110, fin structures are formed on asubstrate, according to some embodiments. As shown in FIG. 2 , multiplefins 204 can be formed on a substrate 202 and protrude from a topsurface of substrate 202. In some embodiments, substrate 202 can be awafer and formed using suitable materials, such as an elementarysemiconductor, a compound semiconductor, an alloy semiconductor, and anysuitable materials. In some embodiments, substrate 202 includes acrystalline silicon substrate (e.g., wafer). In some embodiments,substrate 202 includes (i) an elementary semiconductor, such asgermanium; (ii) a compound semiconductor including silicon carbide,gallium arsenide, gallium phosphide, indium phosphide, indium arsenide,and/or indium antimonide; (iii) an alloy semiconductor including silicongermanium carbide, silicon germanium, gallium arsenic phosphide, galliumindium phosphide, gallium indium arsenide, gallium indium arsenicphosphide, aluminum indium arsenide, and/or aluminum gallium arsenide;or (iv) a combination thereof. Further, substrate 202 can be dopeddepending on design requirements (e.g., p-type substrate or n-typesubstrate). In some embodiments, substrate 202 can be doped with p-typedopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants(e.g., phosphorus or arsenic).

Fins 204 traverse along a Y-axis. Although a pair of fins 204 areillustrated in FIG. 3 , additional fins are formed between the pair offins 204 to form multiple fins and the pair of fins 204 represent theoutermost fins of the multiple fins. The additional fins are referred toherein as inner fins and are not illustrated for simplicity. Outermostfins 204 can have inner sidewalls 204A facing toward the inner fins andouter sidewalls 204B on the opposing side, as shown in FIG. 3 . Innerfins can have inner sidewalls that opposes inner sidewalls from adjacentinner fins and inner sidewalls 204A of outermost fins 204. Top surfacesof fins 204 can be substantially coplanar (e.g., aligned on the samehorizontal plane).

In some embodiments, fins 204 can include material similar to substrate202. In some embodiments, fins 204 can be formed from aphotolithographic patterning and an etching of substrate 202. Based onthe disclosure herein, it will be recognized that other materials forfins 204 are within the scope and spirit of this disclosure. Fins 204are current-carrying structures for finFETs. Channel regions (not shown)of finFETs can be formed in portions of fin structures 204. In someembodiments, each fin of fins 204 can include multiple nanowirestructures (not shown) for forming GAAFET devices. Fins 204 can beformed by etching substrate 202 through patterned first and second hardmask layers 206 and 208 formed on un-etched substrate 202. In someembodiments, first hard mask layer 206 is a thin film including siliconoxide formed using a thermal oxidation process. In some embodiments,second hard mask layer 208 can be formed of silicon nitride using lowpressure chemical vapor deposition (LPCVD) or plasma enhanced CVD(PECVD). In some embodiments, fins 204 can include a top portion 204Ahaving substantially uniform width along the X-axis and a bottom portion204B having a width that gradually changes along the Z-axis.

Referring to FIG. 1 , in operation 120, a shallow trench isolation (STI)material is deposited on the substrate and surrounds the fin structures,according to some embodiments. As shown in FIG. 3 , STI material 310 isdeposited on substrate 202 and surrounds fins 204. STI material 310 caninclude inner portion 310A deposited on substrate 202 and betweenadjacent fins 204. STI material 310 can also include outer portions 310Bdeposited on substrate 202 and on outer sidewalls of outermost fins 204.Inner portions 310A can be formed between outermost fins and betweenadjacent inner fins formed between the outermost fins. STI material 310can electrically isolate adjacent fins from neighboring active andpassive elements (not illustrated herein) integrated with or depositedonto substrate 202. STI material 310 can be made of a dielectricmaterial. In some embodiments, STI material 310 can include siliconoxide, silicon nitride, silicon oxynitride, fluorine-doped silicateglass (FSG), a low-k dielectric material, and/or other suitableinsulating material. In some embodiments, STI material 310 can be formedby depositing a flowable dielectric material, such as flowable siliconoxide, flowable silicon nitride, flowable silicon oxynitride, flowablesilicon carbide, or flowable silicon oxycarbide. For example, flowablesilicon oxide can be deposited using flowable CVD (FCVD). In someembodiments, STI material 310 can be deposited using other suitable CVDprocesses, physical vapor deposition (PVD), atomic layer deposition(ALD), or any suitable deposition processes. A planarization process canbe used after the deposition of STI material 310 to remove hard masklayers 206 and 208 such that top surfaces of fins 204 and STI material310 are substantially coplanar (e.g., level with each other).

Referring to FIG. 1 , in operation 130, the shallow trench isolation(STI) material is etched back using one or more etching processes andtreatment processes, according to some embodiments. An exemplaryoperation 130 can include operation 132 which includes performing afirst etching process, operation 134 which includes performing a secondetching process, and operation 136 which includes an optional radicaltreatment process 136. Operations 132 and 134 can remove STI material310 at different etching rates depending on the location of the targetedSTI material. For example, operation 132 can be a thermal etchingprocess that etches outer portions 310B of STI material 310 at a greateretching rate than inner portions 310A of STI material 310. In contrast,operation 134 can be a plasma-activated etching process that removesinner portions 310A at a greater rate than removing outer portions 310B.The etching and treatment processes described in operation 130 can beperformed in a different order or not performed depending on specificapplications.

Referring to FIG. 1 , in operation 132, a first etching process isperformed, according to some embodiments. As shown in FIG. 4 , a firstetching process 402 can be performed to etch back a portion of STImaterial 310. In some embodiments, first etching process 402 can be athermal etching process using ammonia (NH₃) and hydrogen fluoride (HF)as precursors. First etching process 402 can be a non-plasma etchingprocess and performed at an elevated temperature. First etching process402 can etch STI material 310 at different rates depending on thelocation of the targeted STI material. For example, the etching rate E₁of first etching process 402 in outer portions 310B of STI material 310is greater than the etching rate E₂ for inner portions 310A of STImaterial 310. The etching rate difference can be attributed to thepattern loading effect, a phenomenon that is derived from differences inradiant energy absorption in different areas of a semiconductor deviceor die on account of the different patterning (e.g., pattern density,aspect ratio of features, composition/reflectivity of features, etc.).In some embodiments, a ratio N₁ of etching rate E₁ over etching rate E₂can be about 1 and about 2, or any suitable ratios. For example, ratioN₁ can be greater than or equal to about 1 and less than about 2.Etching rate differences greater than the aforementioned ranges of N₁can lead to etching non-uniformity that can be challenging to address.The value of ratio N₁ can depend on the separation between adjacent finsof multiple fins. Decreasing the separation between fins can result in agreater etch rate difference between etching rates E₁ and E₂. Theprecursor flow rates and etching temperature can be adjusted such thatthe ratio N₁ is within the aforementioned ranges.

First etching process 402 can proceed until a nominal etching height ofSTI material is removed. In some embodiments, the height of STI materialremoved from outer portions 310B of STI material can be denoted as H₁,measured from top surfaces of fins 204 and a top planar surface ofetched outer portions 310B. Similarly, the height of STI materialremoved from inner portions 310A of STI material can be denoted as H₂,measured from top surfaces of fins 204 and a top planar surface ofetched inner portions 310A. In some embodiments, a total height of STImaterial to be removed can be denoted as H, measured from a top surfaceof fins 204 and a targeted top surface of remaining STI material. Insome embodiments, a ratio N₂ of heights H₁ over H₂ can be equal to ratioN₁. In some embodiments, first etching process 402 can remove themajority of the total STI to be removed. In some embodiments, a ratio N₃of height H₁ over total height H can be between about 0.65 and about0.90. A value of ratio N₃ outside of the aforementioned ranges canresult in limited device performance gain or lower yield.

In some embodiments, gas sources can dispense precursors atpredetermined flow rates for first etching process 402. For example, agas source can dispense ammonia precursors into an etching chamber at aflow rate of from about 5 standard cubic centimeters per minute (sccm)to about 110 sccm, from about 10 sccm to about 100 sccm, or any suitableflow rates. The gas source can also dispense hydrogen fluorideprecursors at a flow rate of from about 80 sccm to about 1200 sccm, fromabout 90 sccm to about 1100 sccm, from about 100 sccm to about 1000sccm, or any suitable flow rates. Values of flow rates that are outsidethe aforementioned ranges can result in limited device performance gainor lower yield. In some embodiments, the etching chamber can be achamber configured to conduct a Siconi etching process (e.g., aplasma-assisted dry etching process). In some embodiments, STI material310 can be formed using silicon oxide. Chemical reactions during firstetching process 402 can include generating ammonium fluoride (NH₄F)molecules using the dispensed precursors. When exposed to ammoniumfluoride molecules, the silicon oxide material of STI material 310 canreact to generate ammonium hexafluorosilicate ((NH₄)₂SiF₆) which in turnreacts with water and generates byproducts of silicon tetrafluoride(SiF₄). Some of the chain chemical reactions of first etching process402 can be represented using the following chemical representations:NH₃+HF→NH₄F and SiO₂+NH₄F→(NH₄)₂SiF₆+H₂O→SiF₄(g)+NH₃(g)+HF(g).

In some embodiments, first etching process 402 can be performed at atemperature between about 25° C. and about 50° C. For example, theetching chamber used to perform first etching process 402 can bemaintained at a temperature between about 25° C. and about 30° C.,between about 30° C. and about 35° C., between about 35° C. and about40° C., between about 40° C. and about 45° C., between about 45° C. andabout 50° C., or any suitable temperatures. Temperatures below or abovethe aforementioned ranges can cause low chemical reactivity of theprecursors which can in turn lead to low etching rates or ineffectiveetching.

Referring to FIG. 1 , in operation 134, a second etching process isapplied to further remove STI material, according to some embodiments.As shown in FIG. 5 , a second etching process 502 can be performed tofurther etch back STI material 310. In some embodiments, second etchingprocess 502 can be a plasma-activated etching process using ammonia(NH₃) and nitrogen trifluoride (NF₃) as precursors. Second etchingprocess 502 can be a plasma-activated etching process using a plasmaetching apparatus. The plasma can be generated in a plasma generationprocess by a plasma generator such as a transformer-coupled plasmagenerator, inductively coupled plasma system, magnetically enhancedreactive ion etching system, electron cyclotron resonance system, remoteplasma generator, or the like. The plasma generator generates radiofrequency power that produces a plasma from ammonia and nitrogentrifluoride fluoride, such as by applying a voltage above the strikingvoltage to electrodes in a chamber containing the precursors. Comparedto first etching process 402, second etching process 502 can remove STImaterial 310 at lower rates on outer portions than inner portions of STImaterial, according to some embodiments. For example, the etching rateE₃ of second etching process 502 in outer portions 310B of STI material310 can be lower than the etching rate E₄ for inner portions 310A. Theetching rate difference can be attributed to the generation of ammoniafluoride radicals that can assist in etching in tight spaces, such asthe STI material located between adjacent fins. In some embodiments,remnant traces of oxygen in the process chamber can form a layer ofnative oxide on fins 204 during first and second etching processes 402and 502. Plasma species used in second etching process 502 (e.g., NH₃and NF₃) can etch native oxide at an etching rate that is slower thanplasma species used in first etching process 402 (e.g., NH₃ and HF),therefore providing more radicals in the tight spaces between fins forincreasing the etching rate of STI material 310. In some embodiments, aratio N₄ of etching rate E₃ over etching rate E₄ can be less than orequal to 1 and greater than about 0.5. Etching rate differences greaterthan the aforementioned ranges of N₄ can lead to challenges in providinga substantially uniform etch across multiple fins. The precursor flowrates and plasma intensity can be adjusted such that the ratio N₄ iswithin the aforementioned ranges. Second etching process 502 can proceeduntil a nominal etching height of STI material is removed. In someembodiments, the height of STI material removed from outer portions 310Bof STI material during second etching process 502 can be denoted as H₃.Similarly, the height of STI material removed from inner portions 310Aof STI material during second etching process 502 can be denoted as H₄.In some embodiments, a ratio N₅ of heights H₃ over H₄ can be equal toratio N₄. In some embodiments, second etching process 502 can remove asmaller amount of STI material than first etching process 402. In someembodiments, a ratio N₆ of height H₃ over total height H can be betweenabout 0.10 and about 0.35. In some embodiments, second etching process502 can be used to counter the surface unevenness (e.g., differences inheights H₁ and H₂) caused by first etching process 402 such that afterfirst and second etching process 402 and 502, the top surfaces of innerportions 310A and outer portions 310B are substantially coplanar (e.g.,level). Second etching process can continue until a nominal fin height(e.g., height of fin 204 protruding from STI material 310) or until thetop surfaces of inner and outer portions 310A and 310B are substantiallycoplanar. In some embodiments, second etching process can proceed untiltop surfaces of inner portions 310A are lower than top surfaces of outerportions 310B.

In some embodiments, gas sources can dispense precursors atpredetermined flow rates for second etching process 502. For example, agas source can dispense ammonia precursors into an etching chamber at aflow rate of from about 5 sccm to about 320 sccm, from about 7 sccm toabout 310 sccm, from about 10 sccm to about 300 sccm, or any suitableflow rates. The gas source can also dispense nitrogen trifluorideprecursors at a flow rate of from about 35 sccm to about 600 sccm, fromabout 40 sccm to about 550 sccm, from about 50 sccm to about 500 sccm,or any suitable flow rates. In some embodiments, STI material 310 can beformed using silicon oxide. Chemical reactions during second etchingprocess 502 can include generating ammonium fluoride (NH₄F) radicals aswell as ammonium fluoride molecules using the dispensed precursors andunder plasma. When exposed to ammonium fluoride molecules and radicals,the silicon oxide material of STI material 310 can react to generateammonium hexafluorosilicate which in turn reacts with water and generatebyproducts of silicon tetrafluoride. Some of the chain chemicalreactions of second etching process 502 can be represented using thefollowing chemical representations: NH₃+NF₄→plasma (RF)→NH₄F+NH₄F·HF andSiO₂+NH₄F→(NH₄)₂SiF₆+H₂O→SiF₄(g)+NH₃(g)+HF(g). In some embodiments, ananneal process can be used during or after the etching process. Forexample, an annealing process can be performed to enhance the generationof silicon tetrafluoride gas. In some embodiments, the anneal processcan be performed at a temperature between about 30° C. and about 80° C.Annealing processes performed at a temperature below about 30° C. canlead to insufficient sublimation of (NH₄)₂SiF₆, which in turn can resultin poor etching performance (e.g., residue or defect generation).Annealing processes performed at temperatures greater than about 80° C.can result in unstable plasma species which in turn can lead to plasmadegradation.

In some embodiments, second etching process 502 can be performed in aplasma chamber. A radio frequency (RF) source can be applied to theplasma chamber to excite the ions from precursors and create plasma. Thepower of the RF source can be between about 25 W and about 75 W. Forexample, the power can be between about 25 W and about 40 W, betweenabout 40 W and about 50 W, between about 50 W and about 75 W, or anysuitable RF power. RF power below the aforementioned ranges can causelow chemical reactivity of the precursors which can in turn lead to lowetching rates or ineffective etching. RF power greater than theaforementioned ranges can lead to challenges in providing a consistentetching rate.

Referring to FIG. 1 , in operation 136, a radical treatment process isapplied to on the STI material, according to some embodiments. As shownin FIG. 6 , a radical treatment process 602 is applied to the topsurfaces of STI material 310. In some embodiments, radical treatmentprocess can be optional. The radical treatment process can be a hydrogenradical treatment process, in which surfaces of STI material 310 areexposed to hydrogen radicals. Hydrogen radicals readily react with GroupIV materials to form tetrahydride compounds. The hydrogen radicaltreatment process can be performed in a chamber, such as an etchingchamber. In some embodiments, radical treatment process 602 can beperformed in the processing chambers used to perform first and secondetching processes 402 and 502. In some embodiments, radical treatmentprocess 602 can be a plasma-assisted radical treatment process. Forexample, the plasma-assisted radical treatment process can use hydrogenor helium as precursors. For example, one or more gas sources aredispensed in the etching chamber. The gas source includes a precursorgas and an inert gas. The precursor gas can include hydrogen (H₂), andthe inert gas can include argon (Ar), helium (He), or a combinationthereof. A plasma is generated after the precursor gases are dispensedinto the processing chamber. The plasma can be generated in a plasmageneration process by a plasma generator. When exposed to the hydrogenplasma, the material (e.g., silicon oxide) at the surface of the STImaterial 310 breaks apart and recombines with the free hydrogen ions toform silane (SiH₄) and water (H₂O), thus removing the dielectricmaterial at top surfaces of STI material 310. The byproducts can beremoved from the processing chamber during their formation by vacuuming.As shown in FIG. 6 , dielectric material can be uniformly removed frominner portions 310A and outer portions 310B of STI material 310. In someembodiments, the height of STI material removed from inner portions 310Aand outer portions 310B of STI material during radical treatment process602 can be denoted as H₅. In some embodiments, a ratio N₇ of height H₅over total height H can be less than about 0.05.

FIGS. 7-11 are flow diagrams of methods for etching back STI material toexpose multiple fins, according to some embodiments. For illustrativepurposes, the operations illustrated in FIGS. 7-11 can be similar tothose illustrated in FIGS. 2-6 . For example, each of the methodsdescribed in FIGS. 7-11 can be used for performing operation 130described in FIG. 1 . Operations can be performed in a different orderor not performed depending on specific applications. It should be notedthat the methods described in FIGS. 7-11 are for etching back STImaterial and may not produce a complete semiconductor device.Accordingly, it is understood that additional processes can be providedbefore, during, and after the methods disclosed herein, and that someother processes may only be briefly described.

Referring to FIG. 7 , method 700 can include operation 702 that includesa plasma-activated etching process, operation 704 that includes athermal etching process, and operation 706 that includes a radicaltreatment process. In some embodiments, the plasma-activated etchingprocess in operation 702 can be similar to second etching processdescribed with reference to FIG. 5 . For example, the plasma-activatedetching process in operation 702 can have different etching rates oninner portions and outer portions of the STI material. In someembodiments, the removed material from the outer portions of the STImaterial can have a height between about 10% and 35% of the total heightof the STI material to be removed. In some embodiments, the thermaletching process of operation 704 can be similar to first etching process402 described in FIG. 4 . For example, the thermal etching process ofoperation 704 can remove STI material at a greater rate in the outerportions of the STI material than the inner portions of the STImaterial. In some embodiments, the removed material from the outerportions of the STI material during operation 704 can be between about65% and about 90% of the total height of the STI material to be removed.Second operations 702 and 704 can be followed by operation 706 whichincludes performing a radical treatment process that is similar toradical treatment process 602 described in FIG. 6 . For example, ahydrogen radical treatment process can be performed to further removeSTI material. After the operations described in method 700, the topsurfaces of inner portions and outer portions of etched-back STImaterial can be substantially coplanar. In some embodiments, topsurfaces of the inner portions can be lower than the top surfaces of theouter portions.

Referring to FIG. 8 , method 800 can include operation 802 that includesa thermal etching process, operation 804 that includes a radicaltreatment process, and operation 806 that includes a plasma-activatedetching process. In some embodiments, the thermal etching process ofoperation 802 can be similar to first etching process 402 described inFIG. 4 . For example, the thermal etching process of operation 802 canremove STI material at a greater rate in the outer portions of the STImaterial than the inner portions of the STI material. In someembodiments, the removed material from the outer portions of the STImaterial during operation 802 can be between about 65% and about 90% ofthe total height of the STI material to be removed. Operation 804 caninclude a radical treatment process that is similar to radical treatmentprocess 602 described in FIG. 6 . For example, a hydrogen radicaltreatment process can be performed to further remove STI material. Insome embodiments, the plasma-activated etching process in operation 804can be similar to second etching process 502 described with reference toFIG. 5 . For example, the plasma-activated etching process in operation804 can have different etching rates on inner portions and outerportions of the STI material. In some embodiments, the removed materialfrom the outer portions of the STI material can have a height betweenabout 10% and 35% of the total height of the STI material to be removed.

Referring to FIG. 9 , method 900 can include operation 902 that includesa plasma-activated etching process, operation 904 that includes aradical treatment process, and operation 906 that includes a thermaletching process. In some embodiments, the plasma-activated etchingprocess in operation 902 can be similar to second etching process 502described with reference to FIG. 5 . For example, the plasma-activatedetching process in operation 902 can have different etching rates oninner portions and outer portions of the STI material. In someembodiments, the removed material from the outer portions of the STImaterial can have a height between about 10% and 35% of the total heightof the STI material to be removed. Operation 904 can include a radicaltreatment process that is similar to radical treatment process 602described in FIG. 6 . For example, a hydrogen radical treatment processcan be performed to further remove STI material. In some embodiments,the thermal etching process of operation 906 can be similar to firstetching process 402 described in FIG. 4 . For example, the thermaletching process of operation 906 can remove STI material at a greaterrate in the outer portions of the STI material than the inner portionsof the STI material. In some embodiments, the removed material from theouter portions of the STI material during operation 906 can be betweenabout 65% and about 90% of the total height of the STI material to beremoved.

Referring to FIG. 10 , method 1000 can include operation 1002 thatincludes a thermal etching process, operation 1004 that includes a firstradical treatment process, operation 1006 that includes aplasma-activated etching process, and operation 1008 that includes asecond thermal etching process. In some embodiments, the thermal etchingprocess of operation 1002 can be similar to first etching process 402described in FIG. 4 . For example, the thermal etching process ofoperation 1002 can remove STI material at a greater rate in the outerportions of the STI material than the inner portions of the STImaterial. In some embodiments, the removed material from the outerportions of the STI material during operation 1002 can be between about65% and about 90% of the total height of the STI material to be removed.Operation 1004 can include a first radical treatment process that issimilar to radical treatment process 602 described in FIG. 6 . Forexample, a hydrogen radical treatment process can be performed tofurther remove STI material. In some embodiments, the plasma-activatedetching process in operation 1006 can be similar to second etchingprocess 502 described with reference to FIG. 5 . For example, theplasma-activated etching process in operation 1006 can have differentetching rates on inner portions and outer portions of the STI material.In some embodiments, the removed material from the outer portions of theSTI material can have a height between about 10% and 35% of the totalheight of the STI material to be removed. In some embodiments, thesecond radical treatment process in operation 1008 can be similar tofirst radical treatment in operation 1004. In some embodiments, each ofthe first and second radical treatment processes in operations 1004 and1008 can etch back about 1% to about 5% of the total STI material to beremoved.

Referring to FIG. 11 , method 1100 can include operation 1102 thatincludes a plasma-activated etching process, operation 1104 thatincludes a first radical treatment process, operation 1106 that includesa thermal etching process, and operation 1108 that includes a secondradical treatment process. In some embodiments, the plasma-activatedetching process in operation 1102 can be similar to second etchingprocess 502 described with reference to FIG. 5 . For example, theplasma-activated etching process in operation 1102 can have differentetching rates on inner portions and outer portions of the STI material.In some embodiments, the removed material from the outer portions of theSTI material can have a height between about 10% and 35% of the totalheight of the STI material to be removed. Operation 1104 can include afirst radical treatment process that is similar to radical treatmentprocess 602 described in FIG. 6 . For example, a hydrogen radicaltreatment process can be performed to further remove STI material. Insome embodiments, the thermal etching process of operation 1106 can besimilar to first etching process 402 described in FIG. 4 . For example,the thermal etching process of operation 1106 can remove STI material ata greater rate in the outer portions of the STI material than the innerportions of the STI material. In some embodiments, the removed materialfrom the outer portions of the STI material during operation 1002 can bebetween about 65% and about 90% of the total height of the STI materialto be removed. In some embodiments, the second radical treatment processin operation 1108 can be similar to first radical treatment in operation1104. In some embodiments, each of the first and second radicaltreatment processes in operations 1104 and 1108 can etch back about 1%to about 5% of the total STI material to be removed.

The thermal etching processes and plasma-activated etching process canprovide etched-back STI material with substantially coplanar topsurfaces. In some embodiments, the etching processes can also provideinner portions of etched-back STI material with top surfaces that arelower than the top surfaces of the outer portions of the etched-back STImaterial. As shown in FIG. 12 , a top surface of inner portions 310A canbe lower than a top surface of outer portion 310B. For example, a heightH₆ of STI material removed from between fins 204 can be greater thanheight H of the STI material removed from the outside of fins 204. Insome embodiments, a ratio of H₆ over H can be greater than or equal toabout 1 and less than about 1.2. In some embodiments, a differencebetween heights H₆ and H can be less than about 5 nm. For example, thedifference can be between about 3 nm and about 5 nm. Increasing thedifference between heights H₆ and H can provide benefits, among otherthings, more effective fin area and less gate-to-channel capacitance (CObetween fin-fin spacing.

Referring to FIG. 1 , in operation 140, structures of semiconductordevices can be formed on the STI material and on the fin structures,according to some embodiments. As shown in FIG. 13 , additionalstructures can be formed on the protruding fins after STI material hasbeen etched back.

FIG. 13 is an isometric view of a semiconductor structure 1300, inaccordance with some embodiments of the present disclosure.Semiconductor structure 1300 includes finFETs that are formed using thefins and STI material formed using the methods and structures describedwith reference to FIGS. 1-12 . For example, semiconductor structure 1300includes substrate 202, multiple fins 204, STI material 310, and a gatestructure 1380. Gate structure 1380 is disposed over sidewalls and a topsurface of each of fins 204. Gate structure 1380 includes a gatedielectric layer 1302 and a gate electrode 1307. In some embodiments,one or more additional layers or structures can be included in gatestructure 1380.

FIG. 13 shows a hard mask 1320 disposed on a top surface of gateelectrode 1307. Hard mask 1320 is used to pattern, such as by etching,gate structure 1380. In some embodiments, hard mask 1320 includes adielectric material, such as silicon nitride. The isometric view of FIG.13 is taken after the patterning process (e.g., etching) of a gatedielectric layer and a gate electrode layer to form gate structure 1380.Integrated circuits can include multiple of such, and similar, gatestructures.

Each of the multiple fins 204 includes a pair of source/drain (S/D)terminals S/D 1308. S/D 1308 are formed in, on, and/or surrounding fins204. A channel region of fins 204 underlies gate structure 1380. S/D1308 can be formed using doped semiconductor material, such as dopedcrystalline silicon. In some embodiments, S/D 1308 can be formed usingsilicon germanium.

STI material 310 can partially fill the recesses and can include adielectric material such as, for example, silicon oxide, spin-on-glass,silicon nitride, silicon oxynitride, fluorine-doped silicate glass(FSG), a low-k dielectric material, other suitable insulating material,and/or combinations thereof. STI material 310 can include a multi-layerstructure such as, for example, a structure with one or more linerlayers. STI material 310 can also be formed by depositing an enhancedgap fill layer using multi-step deposition and treatment process toeliminate voids and seams in the gap fill material. STI material 310 canbe etched back using the methods described in FIGS. 1-12 .

Gate structure 1380 can include a gate dielectric layer 1302, a gateelectrode 1307, and/or one or more additional layers, according to someembodiments. In some embodiments, gate structure 1380 uses polysiliconas gate electrode 1307. Although gate structure 1380 is described asusing polysilicon or amorphous silicon for gate electrode 1307, gatestructure 1380 can be a sacrificial gate structure, such as a gatestructure formed in a replacement gate process for a metal gatestructure. The metal gate structure can include barrier layer(s), gatedielectric layer(s), work function layer(s), fill metal layer(s), and/orother suitable materials for a metal gate structure. In someembodiments, the metal gate structure can include capping layers, etchstop layers, and/or other suitable materials.

P-type and n-type work function metals can be included in the metal gatestructure. A work function is associated with the material compositionof the work function layer. Thus, the material of a work function layercan be chosen to tune its work function so that a desired thresholdvoltage Vth is achieved by a device formed in the respective region.

A fill metal layer can be deposited over the work function metallayer(s). The fill metal layer fills in remaining portions of trenchesor openings formed by removal of the sacrificial gate structure. Thefill metal layer can include Al, W, copper (Cu), and/or other suitablematerials. The fill metal can be formed by ALD, CVD, physical vapordeposition (PVD), plating, other suitable processes, and/or combinationsthereof.

Semiconductor structure 1300 described above includes fins 204 and gatestructure 1380. Semiconductor structure 1300 can include multiple gatestructures 108 formed over fins 204. Semiconductor structure 1300 caninclude additional processing to form various features such as, forexample, lightly-doped-drain (LDD) regions and doped S/D structures. Theterm “LDD region” is used to describe lightly-doped regions disposedbetween a channel region of a transistor and at least one of thetransistor's S/D regions. LDD regions can be formed in fins 204 bydoping. Ion implantation can be used, for example, for the dopingprocess. Other processes can be used for doping the LDD regions.

Various embodiments in the present disclosure describe methods forforming semiconductor devices with substantially uniform STI stepheights. An STI material can be deposited on a substrate and surroundmultiple fins, followed by an etch back process to expose portions ofthe fins. Semiconductor devices formed using the methods disclosedherein can have substantially uniform STI step heights across multiplefins. In some embodiments, an inner STI step height can be substantiallyequal to or less than an outer STI step height. Multiple etchingprocesses can be used to achieve the substantially uniform STI stepheights. For example, the etching back process can include etchingprocesses that removes STI material at different rates depending on thelocation of the targeted STI material. The etched STI material can beexposed to a radical treatment process, which can adjust the surfaceprofile of the STI material as well as further etching the STI material.

In some embodiments, a method includes forming a fin protruding from asubstrate, the fin including a first sidewall and a second sidewallformed opposite to the first sidewall. The method also includesdepositing a shallow-trench isolation (STI) material on the substrate.Depositing the STI material includes depositing a first portion of theSTI material in contact with the first sidewall and depositing a secondportion of the STI material in contact with the second sidewall. Themethod also includes performing a first etching process on the STImaterial to etch the first portion of the STI material at a firstetching rate and the second portion of the STI material at a secondetching rate greater than the first etching rate. The method alsoincludes performing a second etching process on the STI material to etchthe first portion of the STI material at a third etching rate and thesecond portion of the STI material at a fourth etching rate less thanthe third etching rate.

In some embodiments, a method, includes forming a plurality of finsprotruding from a substrate, the plurality of fins including first andsecond outermost fins, wherein: the first outermost fin includes a firstinner sidewall and a first outer sidewall formed opposite to the firstinner sidewall; and the second outermost fin includes a second innersidewall opposing the first inner sidewall and a second outer sidewallformed opposite to the second inner sidewall. The method also includesdepositing a shallow-trench isolation (STI) material on the substrate,including depositing a first portion of the STI material between thefirst and second inner sidewalls and depositing a second portion of theSTI material in contact with the first and second outer sidewalls. Themethod also includes performing a first etching process on the STImaterial to etch the first portion of the STI material at a firstetching rate and the second portion of the STI material at a secondetching rate greater than the first etching rate. The method furtherincludes performing a second etching process on the STI material to etchthe first portion of the STI material at a third etching rate and thesecond portion of the STI material at a fourth etching rate less thanthe third etching rate.

In some embodiments, a semiconductor structure includes a plurality offins protruding from a substrate and including first and secondoutermost fins, wherein: the first outermost fin has first and secondsidewalls opposite to each other; the second outermost fin has third andfourth sidewalls opposite to each other, wherein the second and thirdsidewalls face each other; and the top surfaces of the first and secondoutermost fins are aligned on a horizontal plane. The semiconductorstructure also includes a shallow trench isolation (STI) material on thesubstrate, the STI material includes a first portion in contact with thefirst sidewall and having a first top surface, wherein a first height ismeasured from the first top surface to the horizontal plane. The STImaterial also includes a second portion between the first and secondoutermost fins and having a second top surface, wherein a second heightis measured from the second top surface to the horizontal plane and thesecond height is greater than the first height.

The foregoing disclosure outlines features of several embodiments sothat those skilled in the art may better understand the aspects of thepresent disclosure. Those skilled in the art should appreciate that theymay readily use the present disclosure as a basis for designing ormodifying other processes and structures for carrying out the samepurposes and/or achieving the same advantages of the embodimentsintroduced herein. Those skilled in the art should also realize thatsuch equivalent constructions do not depart from the spirit and scope ofthe present disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

What is claimed is:
 1. A semiconductor structure, comprising: aplurality of fins protruding from a substrate and comprising first andsecond outermost fins, wherein: the first outermost fin comprises firstand second sidewalls opposite to each other; the second outermost fincomprises third and fourth sidewalls opposite to each other, wherein thesecond and third sidewalls face each other; and top surfaces of thefirst and second outermost fins are aligned on a horizontal plane; and ashallow trench isolation (STI) material on the substrate, comprising: afirst portion in contact with the first sidewall and comprising a firsttop surface, wherein a first height is measured from the first topsurface to the horizontal plane; and a second portion between the firstand second outermost fins and comprising a second top surface, wherein asecond height is measured from the second top surface to the horizontalplane and the second height is greater than the first height.
 2. Thesemiconductor structure of claim 1, wherein the second portion is incontact with the second and third sidewalls.
 3. The semiconductorstructure of claim 1, further comprising one or more inner finsprotruding from the substrate and between the first and second outermostfins.
 4. The semiconductor structure of claim 1, wherein a ratio of thesecond height over the first height is greater than or equal to about 1and less than about 1.2.
 5. The semiconductor structure of claim 1,wherein a difference between the second height and the first heightranges from about 3 nm to about 5 nm.
 6. The semiconductor structure ofclaim 1, further comprising source/drain terminals and gate structuresformed on the plurality of fins.
 7. The semiconductor structure of claim1, wherein the plurality of fins protrude from the first and second topsurfaces of the STI material.
 8. The semiconductor structure of claim 1,wherein the STI material comprises silicon oxide.
 9. The semiconductorstructure of claim 1, wherein each of the plurality of fins comprises atop portion having a substantially uniform width and a bottom portionhaving a width that gradually changes vertically.
 10. The semiconductorstructure of claim 9, wherein the first and second portions of the STImaterial are in contact with the bottom portion of the plurality offins.
 11. A semiconductor device, comprising: first and second finsprotruding from a substrate, wherein top surfaces of the first andsecond fins are aligned on a horizontal plane; a shallow trenchisolation (STI) material on the substrate, comprising: an inner portionbetween the first and second fins and comprising a first top surface,wherein a first height is measured between the first top surface and thehorizontal plane; and an outer portion outside of the first and secondfins and comprising a second top surface, wherein a second height ismeasured between the second top surface and the horizontal plane, andwherein the first height is greater than the second height; and a gatestructure on the STI material and the first and second fins.
 12. Thesemiconductor structure of claim 11, wherein the gate structurecomprises a gate dielectric layer on the first top surface, the secondtop surface, and the first and second fins.
 13. The semiconductorstructure of claim 11, further comprising one or more fins protrudingfrom the substrate and between the first and second fins.
 14. Thesemiconductor structure of claim 11, wherein a ratio of the first heightover the second height is greater than or equal to about 1 and less thanabout 1.2.
 15. The semiconductor structure of claim 11, wherein each ofthe first and second fins comprises a top portion having a substantiallyuniform width and a bottom portion having a width that gradually changesvertically.
 16. The semiconductor structure of claim 15, wherein theinner and outer portions of the STI material are in contact with thebottom portion of first and second fins.
 17. A semiconductor device,comprising: first and second fins on a substrate and comprising achannel region and a source/drain region, wherein top surfaces of thefirst and second fins are substantially coplanar; a shallow trenchisolation (STI) material on the substrate and comprising a first portionbetween the first and second fins and a second portion outside the firstand second fins, wherein: the first portion comprises a first topsurface measured a first distance from the top surfaces of the first andsecond fins; the second portion comprises a second top surface measureda second distance from the top surfaces of the first and second fins;the channel region and the source/drain region protrude from the firstand second top surfaces; and the first distance is greater than thesecond distance; and a gate structure on the channel region and thefirst and second top surfaces.
 18. The semiconductor structure of claim17, wherein the first and second fins further comprise a lightly dopedregion between the channel region and the source/drain region.
 19. Thesemiconductor structure of claim 17, further comprising one or more finsprotruding from the substrate and between the first and second fins. 20.The semiconductor structure of claim 17, wherein a ratio of the firstdistance over the second distance is greater than or equal to about 1and less than about 1.2.